1. Field of the Invention
The present invention relates to a timing signal generation apparatus and, in particular, it relates to a timing signal generation apparatus for supplying a timing signal to a solid-state image pick-up device in accordance with set-up information thereof.
2. Description of Related Art
A solid-state image pick-up device such as a video camera and a digital still camera using a solid-state image pick-up element such as a CCD is generally known. Such a solid-state image pick-up device is provided with a control circuit for systematically controlling respective functions of an image pick-up section, a signal processor section, a record processor section and the like, and further with a timing signal generation apparatus, i.e., a so-called timing generator, for generating a timing signal which specifies an operating timing of respective sections.
In the following, a conventional timing generator will be described by referring to the accompanying drawing. FIG. 2 is a schematic block diagram showing a conventional timing generator. In this timing generator shown here, from a count value of a V counter 101 which starts counting as triggered by a vertical synchronizing signal VD and also using a horizontal synchronizing signal HD as a clock, a third decoder 102 generates a decode value of a difference in timing for each vertical transfer mode so as to generate a timing pulse. The timing pulse from the third decoder is selected in response to a control data from a microcomputer (hereinafter referred to as a microcom), and is outputted as a leading edge pulse and/or a trailing edge pulse from a second selector 103. The leading edge pulse and/or the trailing edge pulse outputted from the second selector are outputted via a second JK flip flop 104 as a mask signal of a vertical period. Further, from a count value of an H counter 105 which carries out counting as triggered by a horizontal synchronizing signal HD and also using a master clock signal MCK as a clock at the times of a normal transfer and/or a charge read-out transfer in a vertical transfer mode, a first decoder 106 generates a decode value of a change in timing in the normal transfer and/or the charge read-out transfer in the vertical transfer mode so as to generate a timing pulse therefor. Likewise, from a count value of a high speed counter 107 which carries out counting triggered by a horizontal synchronizing signal HD and also using a master clock signal MCK as a clock at the times of a fast sweep out transfer and a frame shift transfer in a vertical transfer mode, a second decoder 108 generates a decode value of a change in timing in the fast sweep out transfer and the frame shift transfer so as to generate a timing pulse therefor. Timing pulses from the first decoder and the second decoder are selected in response to a control data from the microcomputer, and outputted from a first selector 109 as a leading edge pulse and/or a trailing edge pulse which were masked with the mask signal for the vertical period which was generated by the second JK flip flop as described above. The masked leading edge pulse and/or trailing edge pulse outputted from the first selector are outputted from a first JK flip flop 110 as timing signals XV 1˜4, XSG 1˜2 of the solid-state image pick-up device.